Initially, the memory is the owner of all the data blocks and it retains that ownership when a processor reads a data block and sites its copy in its cache.This protocol permits the processor to modify a data block only if it acquires ownership. The processor modifying the data block broadcast request to other processors present in the system to invalidate the copies of the same data block in their caches.Whenever a processor modifies a data block present in its cache memory, it immediately updates the same data block in the main memory.Now, let us see the second version where the inconsistent copies in other processors caches are invalidated. If yes, the content of that data block is modified as specified in broadcasted data else the broadcasted data is discarded. When the other processors in the system receive the broadcasted modified data they verify whether they have the same data block present in their cache.So the processor that has modified the shared data block, broadcast the modified data to all the other processors in the system. Now other processors with the same data block present in their cache will have inconsistent data.Whenever a processor modifies a shared data block in its cache, it immediately updates the same data block in the main memory.Let us understand the first version where the inconsistent copies of shared data are updated in other caches. The write-through protocols have two versions and those are: So, the main memory here always has consistent data. In write-through protocol when a processor modifies a data block in its cache, it immediately updates the main memory with the new copy of the same data block.
If it wants to read or write/modify this data block it has to send a request to the owner of the same data block.
And whenever a processor requires a data block it first checks it in its own cache memory. If we talk about the cache memory it is subdivided into a number of blocks. But before getting into the protocols we will discuss some terminologies associated to cache coherence problem. Well, this cache coherence problem can be sorted using the protocols discussed below. The figure below shows the cache coherence problem in a multiprocessing environment. And this problem is the cache coherence problem. But, the main memory and other processors’ cache will have the old copy of the shared memory block X. As the processor P1 will have the modified copy of the shared memory block i.e. In case, the processor P1 modifies the copy of shared memory block X present in its cache. The figure below shows how processors P1, P3 & Pn have the copy of shared data block X of main memory in their caches. Processors may share the same data block by keeping a copy of this data block in their cache. Now, keeping a common cache for all the processors will enhance the size of the cache thereby slowing down the performance of the system.įor better performance, each processor implements its own cache. In a multiprocessor environment, all the processors in the system share the main memory via a bus. Content: Cache Coherence in Computer Architecture In this section, we will discuss the cache coherence problem and the protocol for resolving the cache coherence problem.
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